UTTORI ASM · IN DEVELOPMENT

M740 instruction additions

Browse accepted m740 instruction additions mnemonics and addressing forms.

106 mnemonics. Distinctive forms:

Group	Mnemonics / forms
Accumulator bit branch	`BBS0`–`BBS7 A,target`, `BBC0`–`BBC7 A,target`
Zero-page bit branch	`BBS0`–`BBS7 zp,target`, `BBC0`–`BBC7 zp,target`
Bit set/clear	`SEB0`–`SEB7`, `CLB0`–`CLB7`, `RMB0`–`RMB7` on `A` or `zp`
Immediate store	`LDM zp,#value`
Special-page JSR	`JSR $FFnn` (opcode `$22`), `JSR (zp)` (opcode `$02`)
Other	`BRA`, `COM zp`, `RRF zp`, `TST zp`, `CLT`, `SET`, `FST`, `SLW`, `STP`

The complete fixture-backed mnemonic sets are the catalogs dumped from buildInstructionCatalog for each CPU in src/instructions/catalog.ts.