UTTORI ASM · IN DEVELOPMENT

65816 architecture

Assemble 65816 instructions with explicit width state and supported addressing forms.

The default encoder supports the 92 instruction mnemonics (exercised by the parity fixtures) and the standard 65C816 addressing families. Ninety are exposed through the editor catalog. TSB and TRB are also encoded and tested. The wiki's 65816 reference is the recommended hardware companion, including registers, flags, cycles, and opcode behavior.

arch 65816

sep #$20
lda #$80       ; one-byte immediate while M=1
rep #$20
lda #$1234     ; two-byte immediate while M=0

lda [$12],y
sta $7E2000,x
jsl UploadTiles

The encoder tracks SEP and REP changes to the M and X flags so immediate accumulator/index operands receive the expected width. Its pass state resets before each assembly stage.

Try immediate widths

The .a8 and .a16 directives select the assembler's accumulator width for subsequent immediate operands. They do not emit CPU instructions; in a running program, use SEP or REP to make the processor mode agree.

Append .b, .w, .l, or deprecated .d to force byte, word, long, or double-width selection where the instruction supports that size:

lda.b $12
lda.w $0012
lda.l $7E0012

An explicit suffix cannot invent an addressing mode the processor does not possess. Parentheses and brackets still decide indirect forms, and branches still enforce their signed displacement range.

optimize dp none disables direct-page optimization. optimize dp ram and optimize dp always enable it. The initial setting is disabled, making size choice conservative unless the operand spelling or suffix is decisive.